Specialized code paths in gpu processing

ABSTRACT

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of, claims the benefit and priorityto previously filed U.S. patent application Ser. No. 15/089,270 filedApr. 1, 2016, entitled “SPECIALIZED CODE PATHS IN GPU PROCESSING” whichis a continuation of, claims the benefit of U.S. Provisional ApplicationSer. No. 62/269,682 filed Dec. 18, 2015, entitled “Specialized CodePaths,” which application is incorporated herein by reference in theirentireties.

BACKGROUND

A graphics processing unit (GPU), also occasionally called a visualprocessing unit (VPU), is a specialized electronic circuit designed torapidly manipulate and alter memory to accelerate the creation of imagesin a frame buffer intended for output to a display. GPUs are used inembedded systems, mobile phones, personal computers, workstations, andgame consoles. Modern GPUs are very efficient at manipulating computergraphics and image processing, and their highly parallel structure makesthem more effective than general-purpose CPUs for algorithms where theprocessing of large blocks of data is done in parallel. In a personalcomputer, a GPU can be present on a video card, or it can be embedded onthe motherboard, in a System-on-Chip, or in certain CPUs, on the CPU dieitself.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of an operating environment.

FIG. 2 illustrates an embodiment of processor.

FIG. 3 illustrates an embodiment of a graphics processor.

FIG. 4 illustrates an embodiment of a graphics processing engine.

FIG. 5 illustrates an embodiment of a graphics processor.

FIG. 6 illustrates an embodiment of a pixel shader.

FIG. 7 illustrates an embodiment of graphics core instruction formats.

FIG. 8 illustrates an embodiment of a graphics processor.

FIGS. 9A and 9B illustrate embodiments of a graphics processor commandformat.

FIGS. 10 and 10B illustrates an embodiment of a data processing system.

FIG. 11 illustrates an embodiment of an IP core development.

FIG. 12 illustrates an embodiment of an integrated circuit.

FIG. 13 illustrates an embodiment of a first enhanced shader sequence.

FIG. 14 illustrates an embodiment of a second enhanced shader sequence.

FIG. 15 illustrates an embodiment of a first logic flow.

FIG. 16 illustrates an embodiment of a second logic flow.

FIG. 17 illustrates an embodiment of a third logic flow.

DETAILED DESCRIPTION

The present disclosure is generally directed to improved graphicsprocessing techniques, and particularly to improved graphics processingtechniques implemented by one or more graphics processing unit (GPU) toincrease GPU performance, reduce compute cycles, promote efficient useof memory resources, and improve overall user experience when utilizingelectronic devices utilizing the one or more GPUs.

One potential bottle neck associated with a GPU is “shader” executiondue to, for example, limited compute or memory throughput. A shader is acomputer program that is used to do shading, such as the production ofappropriate levels of color within an image, produce special effects orperform video post-processing. To increase performance, graphics driverstypically employ a shader compiler to generate enhanced versions ofshaders to reduce the number of instructions and memory accesses.Classical optimization techniques include optimizing loops, constantfolding and propagation, dead code elimination, and so forth.

The present disclosure provides to improve GPU performance byintroducing enhanced code paths in the shader. More specifically, ashader compiler can provision a shader to enhance processing of frequentand/or common values (e.g., zero, one, black & white color valueswidespread in three dimensional (3D) graphics applications, or thelike). It is noted, graphics applications typically read and computecertain common values (e.g., 0.0f, 1.0f, black, red, white, etc.).Furthermore, there are a subset of GPU shader instructions that can bemonitored to determine where these common values originate. Examplesprovide enhanced code paths in the shader to determine when commonvalues are to be processed and to increase processing efficiency basedon these common values.

As used herein, “common value” can be interpreted as a predeterminedvalue or predetermined values of a set of values. For example, a commonvalue can be a value from a set of values, the set of values to includeone or more values. For example, a common value can be a value from aset of values that comprise one and zero. Although examples hereinprovide the common value, or predetermined value, can be one or zero,examples are not limited in this context.

Embodiments can identify special points in the shader code where commonvalues (e.g., zero, one, or the like) originate. For example, thepresent disclosure can determine common values are to be processed basedon various instructions (e.g., sample_c, mul_sat, add_sat, saturate,sample, or the like). Shader execution following identification ofcommon value processing, or that is, code execution to process theseidentified common values can be enhanced. For example, the presentdisclosure can enhance these code section using techniques such as,constant folding, constant propagation and/or dead code removal. It isworthy to note, the present disclosure may introduce some processingoverhead. In particular, overhead due to, for example, evaluating thevalues that flows through specific points to identify the common valuesand switching between the original code path and the enhanced code pathcan be introduced. However, this overhead can be mitigated and overallshader execution reduced due to execution of the enhanced code paths.

It is worthy to note, the present disclosure can provide improvementsover existing compiler optimization techniques. For instance, onecompiler optimization technique attempts to enhance the shader codesequence without any knowledge of the range of outputs. By introducingspecialized code paths based on this knowledge about instructions thatfrequently generate common values, embodiments can improve bothperformance and efficiency of GPU applications. It is worthy to note,the present disclosure can increase GPU efficiency and reduce shaderexecution times without merely introducing more gates at the GPU.Furthermore, the present disclosure can increase energy efficiency, thatis, potentially provide increased performance per watt as the number ofinstructions and memory accesses when dealing with frequent commonvalues is reduced.

Various embodiments may comprise one or more elements. An element maycomprise any structure arranged to perform certain operations. Eachelement may be implemented as hardware, software, or any combinationthereof, as desired for a given set of design parameters or performanceconstraints. Although an embodiment may be described with a limitednumber of elements in a certain topology by way of example, theembodiment may include more or less elements in alternate topologies asdesired for a given implementation. It is worthy to note that anyreference to “one embodiment” or “an embodiment” means that a particularfeature, structure, or characteristic described in connection with theembodiment is included in at least one embodiment. The appearances ofthe phrases “in one embodiment,” “in some embodiments,” and “in variousembodiments” in various places in the specification are not necessarilyall referring to the same embodiment.

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In general, the processing system 100 can generate and/orexecute enhanced shader(s) (e.g., refer to FIG. 10A to 10B and FIGS. 13to 14) based, in part, on determining common value and insertingenhanced instructions to process the common values (e.g., refer to FIGS.16 to 17). In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In on embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 100 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 100 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 100 can also include, couple with, or be integratedwithin a wearable device, such as a smart watch wearable device, smarteyewear device, augmented reality device, or virtual reality device. Insome embodiments, data processing system 100 is a television or set topbox device having one or more processors 102 and a graphical interfacegenerated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, processor 102 is coupled to a processor bus 110 totransmit communication signals such as address, data, or control signalsbetween processor 102 and other components in system 100. In oneembodiment the system 100 uses an exemplary ‘hub’ system architecture,including a memory controller hub 116 and an Input Output (I/O)controller hub 130. A memory controller hub 116 facilitatescommunication between a memory device and other components of system100, while an I/O Controller Hub (ICH) 130 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 116 is integrated within the processor.

Memory device 120 can be a dynamic random access memory (DRAM) device, astatic random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 120 can operate as system memory for the system 100, to storedata 122 and instructions 121 for use when the one or more processors102 executes an application or process. Memory controller hub 116 alsocouples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations.

In some embodiments, ICH 130 enables peripherals to connect to memorydevice 120 and processor 102 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 146, afirmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi,Bluetooth), a data storage device 124 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 140 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 144 combinations. A network controller 134 mayalso couple to ICH 130. In some embodiments, a high-performance networkcontroller (not shown) couples to processor bus 110. It will beappreciated that the system 100 shown is exemplary and not limiting, asother types of data processing systems that are differently configuredmay also be used. For example, the I/O controller hub 130 may beintegrated within the one or more processor 102, or the memorycontroller hub 116 and I/O controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. In general, the processor 200can generate and/or execute enhanced shader(s) (e.g., refer to FIG. 10Ato 10B and FIGS. 13 to 14) based, in part, on determining common valueand inserting enhanced instructions to process the common values (e.g.,refer to FIGS. 16 to 17). Those elements of FIG. 2 having the samereference numbers (or names) as the elements of any other figure hereincan operate or function in any manner similar to that describedelsewhere herein, but are not limited to such. Processor 200 can includeadditional cores up to and including additional core 202N represented bythe dashed lined boxes. Each of processor cores 202A-202N includes oneor more internal cache units 204A-204N. In some embodiments eachprocessor core also has access to one or more shared cached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 210 provides management functionality forthe various processor components. In some embodiments, system agent core210 includes one or more integrated memory controllers 214 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, a displaycontroller 211 is coupled with the graphics processor 208 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 211 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 208 or system agent core 210.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-N executea first instruction set, while at least one of the other cores executesa subset of the first instruction set or a different instruction set. Inone embodiment processor cores 202A-202N are heterogeneous in terms ofmicroarchitecture, where one or more cores having a relatively higherpower consumption couple with one or more power cores having a lowerpower consumption. Additionally, processor 200 can be implemented on oneor more chips or as an SoC integrated circuit having the illustratedcomponents, in addition to other components.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In general, thegraphics processor 300 can generate and/or execute enhanced shader(s)(e.g., refer to FIG. 10A to 10B and FIGS. 13 to 14) based, in part, ondetermining common value and inserting enhanced instructions to processthe common values (e.g., refer to FIGS. 16 to 17). In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 300 includesa video codec engine 306 to encode, decode, or transcode media to, from,or between one or more media encoding formats, including, but notlimited to Moving Picture Experts Group (MPEG) formats such as MPEG-2,Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well asthe Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1,and Joint Photographic Experts Group (JPEG) formats such as JPEG, andMotion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, graphics processing engine 310 is a compute engine forperforming graphics operations, including three-dimensional (3D)graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the GPE 410 is a version of the GPE 310 shown in FIG. 3.Elements of FIG. 4 having the same reference numbers (or names) as theelements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, GPE 410 couples with a command streamer 403, whichprovides a command stream to the GPE 3D and media pipelines 412, 416. Insome embodiments, command streamer 403 is coupled to memory, which canbe system memory, or one or more of internal cache memory and sharedcache memory. In some embodiments, command streamer 403 receivescommands from the memory and sends the commands to 3D pipeline 412and/or media pipeline 416. The commands are directives fetched from aring buffer, which stores commands for the 3D and media pipelines 412,416. In one embodiment, the ring buffer can additionally include batchcommand buffers storing batches of multiple commands. The 3D and mediapipelines 412, 416 process the commands by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to an execution unit array 414. In some embodiments,execution unit array 414 is scalable, such that the array includes avariable number of execution units based on the target power andperformance level of GPE 410.

In some embodiments, a sampling engine 430 couples with memory (e.g.,cache memory or system memory) and execution unit array 414. In someembodiments, sampling engine 430 provides a memory access mechanism forexecution unit array 414 that allows execution array 414 to readgraphics and media data from memory. In some embodiments, samplingengine 430 includes logic to perform specialized image samplingoperations for media.

In some embodiments, the specialized media sampling logic in samplingengine 430 includes a de-noise/de-interlace module 432, a motionestimation module 434, and an image scaling and filtering module 436. Insome embodiments, de-noise/de-interlace module 432 includes logic toperform one or more of a de-noise or a de-interlace algorithm on decodedvideo data. The de-interlace logic combines alternating fields ofinterlaced video content into a single fame of video. The de-noise logicreduces or removes data noise from video and image data. In someembodiments, the de-noise logic and de-interlace logic are motionadaptive and use spatial or temporal filtering based on the amount ofmotion detected in the video data. In some embodiments, thede-noise/de-interlace module 432 includes dedicated motion detectionlogic (e.g., within the motion estimation engine 434).

In some embodiments, motion estimation engine 434 provides hardwareacceleration for video operations by performing video accelerationfunctions such as motion vector estimation and prediction on video data.The motion estimation engine determines motion vectors that describe thetransformation of image data between successive video frames. In someembodiments, a graphics processor media codec uses video motionestimation engine 434 to perform operations on video at the macro-blocklevel that may otherwise be too computationally intensive to performwith a general-purpose processor. In some embodiments, motion estimationengine 434 is generally available to graphics processor components toassist with video decode and processing functions that are sensitive oradaptive to the direction or magnitude of the motion within video data.

In some embodiments, image scaling and filtering module 436 performsimage-processing operations to enhance the visual quality of generatedimages and video. In some embodiments, scaling and filtering module 436processes image and video data during the sampling operation beforeproviding the data to execution unit array 414.

In some embodiments, the GPE 410 includes a data port 444, whichprovides an additional mechanism for graphics subsystems to accessmemory. In some embodiments, data port 444 facilitates memory access foroperations including render target writes, constant buffer reads,scratch memory space reads/writes, and media surface accesses. In someembodiments, data port 444 includes cache memory space to cache accessesto memory. The cache memory can be a single data cache or separated intomultiple caches for the multiple subsystems that access memory via thedata port (e.g., a render buffer cache, a constant buffer cache, etc.).In some embodiments, threads executing on an execution unit in executionunit array 414 communicate with the data port by exchanging messages viaa data distribution interconnect that couples each of the sub-systems ofGPE 410.

FIG. 5 is a block diagram of another embodiment of a graphics processor500. In general, the graphics processor 500 can generate and/or executeenhanced shader(s) (e.g., refer to FIG. 10A to 10B and FIGS. 13 to 14)based, in part, on determining common value and inserting enhancedinstructions to process the common values (e.g., refer to FIGS. 16 to17). Elements of FIG. 5 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 500 includes a ring interconnect502, a pipeline front-end 504, a media engine 537, and graphics cores580A-580N. In some embodiments, ring interconnect 502 couples thegraphics processor to other processing units, including other graphicsprocessors or one or more general-purpose processor cores. In someembodiments, the graphics processor is one of many processors integratedwithin a multi-core processing system.

In some embodiments, graphics processor 500 receives batches of commandsvia ring interconnect 502. The incoming commands are interpreted by acommand streamer 503 in the pipeline front-end 504. In some embodiments,graphics processor 500 includes scalable execution logic to perform 3Dgeometry processing and media processing via the graphics core(s)580A-580N. For 3D geometry processing commands, command streamer 503supplies commands to geometry pipeline 536. For at least some mediaprocessing commands, command streamer 503 supplies the commands to avideo front end 534, which couples with a media engine 537. In someembodiments, media engine 537 includes a Video Quality Engine (VQE) 530for video and image post-processing and a multi-format encode/decode(MFX) 533 engine to provide hardware-accelerated media data encode anddecode. In some embodiments, geometry pipeline 536 and media engine 537each generate execution threads for the thread execution resourcesprovided by at least one graphics core 580A.

In some embodiments, graphics processor 500 includes scalable threadexecution resources featuring modular cores 580A-580N (sometimesreferred to as core slices), each having multiple sub-cores 550A-550N,560A-560N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 500 can have any number of graphicscores 580A through 580N. In some embodiments, graphics processor 500includes a graphics core 580A having at least a first sub-core 550A anda second core sub-core 560A. In other embodiments, the graphicsprocessor is a low power processor with a single sub-core (e.g., 550A).In some embodiments, graphics processor 500 includes multiple graphicscores 580A-580N, each including a set of first sub-cores 550A-550N and aset of second sub-cores 560A-560N. Each sub-core in the set of firstsub-cores 550A-550N includes at least a first set of execution units552A-552N and media/texture samplers 554A-554N. Each sub-core in the setof second sub-cores 560A-560N includes at least a second set ofexecution units 562A-562N and samplers 564A-564N. In some embodiments,each sub-core 550A-550N, 560A-560N shares a set of shared resources570A-570N. In some embodiments, the shared resources include sharedcache memory and pixel operation logic. Other shared resources may alsobe included in the various embodiments of the graphics processor.

FIG. 6 illustrates thread execution logic 600 including an array ofprocessing elements employed in some embodiments of a GPE. In general,the thread execution logic 600 can generate and/or execute enhancedshader(s) (e.g., refer to FIG. 10A to 10B and FIGS. 13 to 14) based, inpart, on determining common value and inserting enhanced instructions toprocess the common values (e.g., refer to FIGS. 16 to 17). Elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 600 includes a pixel shader602, a thread dispatcher 604, instruction cache 606, a scalableexecution unit array including a plurality of execution units 608A-608N,a sampler 610, a data cache 612, and a data port 614. In one embodimentthe included components are interconnected via an interconnect fabricthat links to each of the components. In some embodiments, threadexecution logic 600 includes one or more connections to memory, such assystem memory or cache memory, through one or more of instruction cache606, data port 614, sampler 610, and execution unit array 608A-608N. Insome embodiments, each execution unit (e.g. 608A) is an individualvector processor capable of executing multiple simultaneous threads andprocessing multiple data elements in parallel for each thread. In someembodiments, execution unit array 608A-608N includes any numberindividual execution units.

In some embodiments, execution unit array 608A-608N is primarily used toexecute “shader” programs. In some embodiments, the execution units inarray 608A-608N execute an instruction set that includes native supportfor many standard 3D graphics shader instructions, such that shaderprograms from graphics libraries (e.g., Direct 3D and OpenGL) areexecuted with a minimal translation. The execution units support vertexand geometry processing (e.g., vertex programs, geometry programs,vertex shaders), pixel processing (e.g., pixel shaders, fragmentshaders) and general-purpose processing (e.g., compute and mediashaders).

Each execution unit in execution unit array 608A-608N operates on arraysof data elements. The number of data elements is the “execution size,”or the number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes single instruction multipledata (SIMD) instructions. The various data elements can be stored as apacked data type in a register and the execution unit will process thevarious elements based on the data size of the elements. For example,when operating on a 256-bit wide vector, the 256 bits of the vector arestored in a register and the execution unit operates on the vector asfour separate 64-bit packed data elements (Quad-Word (QW) size dataelements), eight separate 32-bit packed data elements (Double Word (DW)size data elements), sixteen separate 16-bit packed data elements (Word(W) size data elements), or thirty-two separate 8-bit data elements(byte (B) size data elements). However, different vector widths andregister sizes are possible.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, sampler 610 is included to provide texture sampling for 3Doperations and media sampling for media operations. In some embodiments,sampler 610 includes specialized texture or media sampling functionalityto process texture or media data during the sampling process beforeproviding the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. In some embodiments, thread execution logic 600includes a local thread dispatcher 604 that arbitrates thread initiationrequests from the graphics and media pipelines and instantiates therequested threads on one or more execution units 608A-608N. For example,the geometry pipeline (e.g., 536 of FIG. 5) dispatches vertexprocessing, tessellation, or geometry processing threads to threadexecution logic 600 (FIG. 6). In some embodiments, thread dispatcher 604can also process runtime thread spawning requests from the executingshader programs.

Once a group of geometric objects has been processed and rasterized intopixel data, pixel shader 602 is invoked to further compute outputinformation and cause results to be written to output surfaces (e.g.,color buffers, depth buffers, stencil buffers, etc.). In someembodiments, pixel shader 602 calculates the values of the variousvertex attributes that are to be interpolated across the rasterizedobject. In some embodiments, pixel shader 602 then executes anapplication programming interface (API)-supplied pixel shader program.To execute the pixel shader program, pixel shader 602 dispatches threadsto an execution unit (e.g., 608A) via thread dispatcher 604. In someembodiments, pixel shader 602 uses texture sampling logic in sampler 610to access texture data in texture maps stored in memory. Arithmeticoperations on the texture data and the input geometry data compute pixelcolor data for each geometric fragment, or discards one or more pixelsfrom further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 614 includes or couples to one or more cachememories (e.g., data cache 612) to cache data for memory access via thedata port.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In general, the presentdisclosure can generate enhanced shader(s) (e.g., refer to FIGS. 16 to17) based on the example graphics processor instruction formats 700depicted here. In one or more embodiment, the graphics processorexecution units support an instruction set having instructions inmultiple formats. The solid lined boxes illustrate the components thatare generally included in an execution unit instruction, while thedashed lines include components that are optional or that are onlyincluded in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit format 710. A 64-bit compactedinstruction format 730 is available for some instructions based on theselected instruction, instruction options, and number of operands. Thenative 128-bit format 710 provides access to all instruction options,while some options and operations are restricted in the 64-bit format730. The native instructions available in the 64-bit format 730 vary byembodiment. In some embodiments, the instruction is compacted in partusing a set of index values in an index field 713. The execution unithardware references a set of compaction tables based on the index valuesand uses the compaction table outputs to reconstruct a nativeinstruction in the 128-bit format 710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). For 128-bitinstructions 710 an exec-size field 716 limits the number of datachannels that will be executed in parallel. In some embodiments,exec-size field 716 is not available for use in the 64-bit compactinstruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 722, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode information 726 specifying, for example, whetherdirect register addressing mode or indirect register addressing mode isused. When direct register addressing mode is used, the register addressof one or more operands is directly provided by bits in the instruction710.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode todefine a data access alignment for the instruction. Some embodimentssupport access modes including a 16-byte aligned access mode and a1-byte aligned access mode, where the byte alignment of the access modedetermines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction 710 may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction 710 may use 16-byte-aligned addressing for allsource and destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction 710 directly provide the register address of one ormore operands. When indirect register addressing mode is used, theregister address of one or more operands may be computed based on anaddress register value and an address immediate field in theinstruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

FIG. 8 is a block diagram of another embodiment of a graphics processor800. In general, the thread execution logic 600 can generate and/orexecute enhanced shader(s) (e.g., refer to FIG. 10A to 10B and FIGS. 13to 14) based, in part, on determining common value and insertingenhanced instructions to process the common values (e.g., refer to FIGS.16 to 17). Elements of FIG. 8 having the same reference numbers (ornames) as the elements of any other figure herein can operate orfunction in any manner similar to that described elsewhere herein, butare not limited to such.

In some embodiments, graphics processor 800 includes a graphics pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of graphics pipeline 820 or media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A, 852B via a thread dispatcher831.

In some embodiments, execution units 852A, 852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A, 852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 820. Insome embodiments, if tessellation is not used, tessellation components811, 813, 817 can be bypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A, 852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer/depth 873 in the render output pipeline 870 dispatches pixelshaders to convert the geometric objects into their per pixelrepresentations. In some embodiments, pixel shader logic is included inthread execution logic 850. In some embodiments, an application canbypass the rasterizer 873 and access un-rasterized vertex data via astream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A, 852B and associated cache(s) 851,texture and media sampler 854, and texture/sampler cache 858interconnect via a data port 856 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 854, caches 851, 858 and execution units 852A,852B each have separate memory access paths.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front end 834. In some embodiments, videofront end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 337 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 820 and media pipeline 830 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL) and Open Computing Language (OpenCL)from the Khronos Group, the Direct3D library from the MicrosoftCorporation, or support may be provided to both OpenGL and D3D. Supportmay also be provided for the Open Source Computer Vision Library(OpenCV). A future API with a compatible 3D pipeline would also besupported if a mapping can be made from the pipeline of the future APIto the pipeline of the graphics processor.

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. In general, the depicted command format and sequence can beimplemented to process enhanced shader(s) described herein. The solidlined boxes in FIG. 9A illustrate the components that are generallyincluded in a graphics command while the dashed lines include componentsthat are optional or that are only included in a sub-set of the graphicscommands. The exemplary graphics processor command format 900 of FIG. 9Aincludes data fields to identify a target client 902 of the command, acommand operation code (opcode) 904, and the relevant data 906 for thecommand. A sub-opcode 905 and a command size 908 are also included insome commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B shows an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command is 912 is requiredimmediately before a pipeline switch via the pipeline select command913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930, or the media pipeline 924 beginning at themedia pipeline state 940.

The commands for the 3D pipeline state 930 include 3D state settingcommands for vertex buffer state, vertex element state, constant colorstate, depth buffer state, and other state variables that are to beconfigured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based the particular 3DAPI in use. In some embodiments, 3D pipeline state 930 commands are alsoable to selectively disable or bypass certain pipeline elements if thoseelements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of media pipeline state commands940 are dispatched or placed into in a command queue before the mediaobject commands 942. In some embodiments, media pipeline state commands940 include data to configure the media pipeline elements that will beused to process the media objects. This includes data to configure thevideo decode and video encode logic within the media pipeline, such asencode or decode format. In some embodiments, media pipeline statecommands 940 also support the use one or more pointers to “indirect”state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

FIGS. 10A and 10B illustrates exemplary graphics software architecturefor a data processing system 1000 according to some embodiments. Turningmore specifically to FIG. 10A, in some embodiments, softwarearchitecture includes a 3D graphics application 1010, an operatingsystem 1020, and at least one processor 1030. In some embodiments,processor 1030 includes a graphics processor 1032 and one or moregeneral-purpose processor core(s) 1034. The graphics application 1010and operating system 1020 each execute in the system memory 1050 of thedata processing system. In particular, as described herein, the graphicsapplication 1010 and operating system 1020 can each execute in systemmemory 1050 to generate and/or execute an enhanced shader 1060. Theenhanced shader can include branching and enhanced sequences asdescribed herein (e.g., refer to FIGS. 13 to 14).

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. When the Direct3D API is in use, theoperating system 1020 uses a front-end shader compiler 1024 to compileany shader instructions 1012 in HLSL into a lower-level shader language.The compilation may be a just-in-time (JIT) compilation or theapplication can perform shader pre-compilation. In some embodiments,high-level shaders are compiled into low-level shaders during thecompilation of the 3D graphics application 1010.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

Turning more particularly to FIGS. 10A and 10B, the front-end shadercompiler 1024 and/or the back-end shader compiler 1027 can include acommon value detector 1042 and a code insertion module 1044. In general,the shader compiler 1024/1027 can generate the enhanced shader 1060based on determining points in the shader where common values may beprocessed and adding common value processing instructions to theenhanced shader 1060. Accordingly, during operation, a GPU (e.g., anyone or more of the graphics processors described herein) can execute theenhanced shader 1060. The common value detector 1042 can determinespecific points within the shader instructions 1012 where common valuesmay be processed (e.g., refer to FIGS. 15 to 17) and the code insertionmodule 1044 can add enhanced instructions to process the common values(e.g., refer to FIGS. 15 to 17).

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11 is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IPcore. A register transfer level (RTL) design can then be created orsynthesized from the simulation model 1100. The RTL design 1115 is anabstraction of the behavior of the integrated circuit that models theflow of digital signals between hardware registers, including theassociated logic performed using the modeled digital signals. Inaddition to an RTL design 1115, lower-level designs at the logic levelor transistor level may also be created, designed, or synthesized. Thus,the particular details of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3 ^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. The exemplary integrated circuitincludes one or more application processors 1205 (e.g., CPUs), at leastone graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.The integrated circuit includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

Additionally, other logic and circuits may be included in the processorof integrated circuit 1200, including additional graphicsprocessors/cores, peripheral interface controllers, or general purposeprocessor cores.

FIGS. 13 and 14 illustrates exemplary enhanced shader sequences 1300 and1400, respectively; which sequences can be generated and/or executedaccording to embodiments of the present disclosure. The enhanced shadersequences 1300 and 1400 can correspond to the enhanced shader 1060depicted in FIG. 10A. Furthermore, it is noted, the sequences 1300 and1400 are described with reference to the data processing system 1000 ofFIGS. 10A to 10B. However, examples are not limited in this context andthe sequences 1300 and/or 1400 could be implemented by any graphicsprocessors, such as, the graphics processors described herein,

Turning more specifically to FIG. 13, the enhanced shader sequence 1300is depicted. The enhanced shader sequence 1300 may begin at block 1310.At block 1310 “evaluate coordinates” the graphics processor 1032 canevaluate a coordinate as part of a shading function. For example, asdescribed herein, shaders can perform coordinate space transformationsto yield various coordinates (e.g., x, y, z, u, v, or the like) used inimplementing shading functions.

Continuing to block 1320 “implement a shader instruction based on thecoordinates” the graphics processor 1032 can implement a shaderinstruction based on the coordinates evaluated at block 1310. It isworthy to note, that in general, the shader instruction implemented atblock 1320 can be any shader instruction. However, in some embodiments,the shader instruction implemented at block 1320 can be a shaderinstruction in which common values (e.g., zero, one, or the like) areroutinely output. For example, the following exemplary, but notexhaustive, set of six shader instructions can routinely produce commonvalues (e.g., zero, one, or the like): The saturate instruction, whichclamps the specified value within the range of zero to one; the sample_cinstruction, which for each comparison that passes returns 1.0f and foreach comparison that fails returns 0.0f; the mul_sat/add_satinstruction, which multiplies or adds two values and clamp the outputwithin the range zero to one; the ld/sample instruction, which performsa texture lookup; the and instruction, which performs a Boolean AND oftwo operands and necessarily will return zero when one operand is zero;and the ge/eq/le instructions, which implement a greater than, equal to,or less than function and can return a zero or a one. As noted, theseexamples are not exhaustive not intended to be limiting but insteadgiven to provide an illustrative disclosure.

As used herein, “shader instruction” can mean a single shaderinstruction corresponding to a single computational event or can mean agroup or collection of shader instructions corresponding to a sequenceof events. Examples are not limited in this context.

Continuing to block 1330 “instruction output a common value?” thegraphics processor 1032 can determine whether the instruction outputequals a common value. For example, the graphics processor can determinewhether instruction output equals a zero, one, or the like. From block1330, the sequence 1300 can continue to either block 1340 or block 1350.In particular, the sequence 1300 can continue from block 1330 to block1340 based on a determination that the instruction output is not acommon value; while the sequence 1300 can continue from block 1330 toblock 1350 based on a determination that the instruction output is acommon value.

In general, at block 1340 “original sub-sequence” the graphics processor1032 can execute an original shader sub-sequence” while at block 1350“enhance sub-sequence” the graphics processor 1032 can execute anenhanced shader sub-sequence. Examples of the original and enhancedsub-sequences are given below for purposes of explanation. Furthermore,examples for determining an enhanced sub-sequence and insertion pointsin the shader for branches (e.g., block 1330) are also given below. Ingeneral, however, the enhanced sub-sequence 1350 can consume and/orrequire less computing (e.g., graphics processing) resources than theoriginal sub-sequence 1340.

Accordingly, in general, the overall sequence 1300 may be moreefficiently processed by a graphics processor (e.g., the graphicsprocessor 1032, or the like) than conventional shader sequences due tothe efficiencies introduced by processing common values.

Turning more specifically to FIG. 14, the enhanced shader sequence 1400is depicted. It is noted, that the enhanced shader sequence providesillustrative examples (described in greater detail herein) for each ofthe depicted individual operations of the sequences. However, theseexamples are given for illustration only and not to be limiting. Inparticular, the coordinates and/or variables indicated and themathematical operations depicted are done so for purposes of explanationonly. The sequence 1400 could be implemented using different operationsthan depicted.

The enhanced shader sequence 1400 may begin at block 1410. At block 1410“evaluate coordinates” the graphics processor 1032 can evaluate acoordinate as part of a shading function. For example, the graphicsprocessor 1032 can evaluate coordinates u=r0 and v=sqrt(r1).

Continuing to block 1420 “implement a shader instruction based on thecoordinates” the graphics processor 1032 can implement a shaderinstruction based on the coordinates evaluated at block 1310. Forexample, the graphics processor 1032 can determine r6=sample_c(u,v). Asnoted above, the sample_c instruction returns either a 1 or a 0.

Continuing to block 1430 “instruction output a common value?” thegraphics processor 1032 can determine whether the instruction outputequals a common value. For example, the graphics processor can determinewhether instruction output equals a zero. More specifically, theinstruction output can determine whether r6==0. From block 1430, thesequence 1400 can continue to either block 1440 or block 1450. Inparticular, the sequence 1400 can continue from block 1430 to block 1440based on a determination that r6 does not equal zero; while the sequence1400 can continue from block 1430 to block 1450 based on a determinationthat r6 does equal zero.

In general, at block 1440 “original sub-sequence” the graphics processor1032 can execute an original shader sub-sequence” while at block 1450“enhanced sub-sequence” the graphics processor 1032 can execute anenhanced shader sub-sequence. For example, at block 1440, the graphicsprocessor can determine:

r9=r6*r2

r9=sqrt(r9)*Id(u,v)

o0=r9*cb[3],

while, at block 1450 the graphics processor can determine o0 equals 0.Accordingly, in general, the overall sequence 1400 may be moreefficiently processed by a graphics processor (e.g., the graphicsprocessor 1032, or the like) than conventional shader sequences due tothe efficiencies introduced by the enhanced sub-sequence 1450 executedwhen r6 equals zero.

FIGS. 15 to 17 illustrate example logic flows to determine an enhancedshader including an enhanced shader sequences (e.g., 1300, 1400, or thelike) according to embodiments of the present disclosure. In general,any shader compiler can implement the depicted logic flows to generatean enhanced shader. However, examples are described herein inconjunction with the shader compiler 1024 and the enhanced shader 1060for illustration purposes only. This is not to be limiting.

Turning more specifically to FIG. 15, which illustrates a logic flow1500. The shader compiler 1024 can implement logic flow 1500 to generateenhanced shader 1060. In general, the shader compiler 1024 inimplementing logic flow 1500 analyzes an input shader at multiple stepsto see if it can produce common values (e.g., zero, one, or the like)and generates an enhanced sub-sequence (e.g., sub-sequence 1350, 1450,or the like) for the steps that can produce a common value.

Logic flow 1500 can begin at block 1502. At block 1502, operations tocompile a pixel shader are initiated. Continuing to block 1504 “processnext instruction,” shader compiler 1024 can process a next instructionfor the pixel shader. For example, shader compiler 1024 can process anext instruction from the shader instructions 1012.

Continuing to decision block 1506 “can instruction output a commonvalue?” the shader compiler can determine whether the instruction canoutput a common value (e.g., zero, one, or the like). From decisionblock 1506, the logic flow 1500 can continue to either block 1508 ordecision block 1510. In particular, the logic flow 1500 can continuefrom decision block 1506 to block 1508 based on a determination that theinstruction cannot output a common value while the logic flow 1500 cancontinue to decision block 1510 based on a determination that theinstruction can output a common value.

At block 1508 “compile instructions as usual,” the shader compiler 1024can compile the shader instructions 1012 as usual (e.g., conventionally,without enhanced branching, or the like). At decision block 1510 “caninstruction be folded?” the shader compiler 1024 can determine whetherthe instruction that can output a common value can be enhanced (e.g.,folded, or the like). From decision block 1510, the logic flow 1500 cancontinue to either block 1508 or block 1512. In particular, the logicflow 1500 can continue from decision block 1510 to block 1508 based on adetermination that the instruction cannot be enhanced while the logicflow 1500 can continue to block 1512 based on a determination that theinstruction can be enhanced.

At block 1512 “compile instructions with enhanced branch,” the shadercompiler 1024 can compile the shader instructions with an enhancedbranch where the instructions output is a common value (e.g., thesequence 1300, 1400, or the like).

In some examples, at decision block 1510, the shader compiler 1024 candetermine whether the instruction can be “significantly” enhanced, orwhether more than a threshold number of instructions can be foldedand/or enhanced to introduce above a threshold level of efficiency intothe overall shader processing.

In some examples, the shader compiler 1024 can restricts the number ofoptimizations (e.g., enhanced sub-sequences 1350, 1450, or the like) toless than a threshold number to control the overhead of branchingintroduced as a result of the optimization. In some examples, the shadercompiler 1024 can, if possible, predicate the shader instructionsfollowing the instruction that can output a common value.

It is noted, graphics application program interfaces (APIs) (e.g.,Direct3D11(D3D11), or the like) can enable rendering of translucentobjects with the use of a pipeline stage called an OM stage. Typically,OM uses the colors at sample locations in the frame buffer (dest) andblends them with the color generated as a result of pixel shading (src)and blends them using the OM state. To achieve this, OM fetches the datafrom the destination to do the blending and writes out the newlycalculated color (after blending) to the render target. Thisread-modify-write operation can be expensive from a power point of view.

Current shader compilers, however, typically do not enhance codegeneration for a particular value of an OM state. So when an OM state isset to a src_alpha (or “over”) operator, even if the src_alpha is zero,the pixel shader still executes to evaluate src_color. Similarly,workloads can be constructed for testing other cases as well.

FIGS. 16 to 17 depicts logic flows 1600 and 1700, respectively, toenhance shader instructions to reduce and/or or omit read/writeoperations depending on the OM state and an alpha value produced by theshader. It is worthy to note, this optimization can reduce bandwidthrequirements for executing the shader. In general, the shaderinstructions used to evaluate color in such situations can be omitted.In particular, the enhanced shader can use a conditional to generate acompiled shader to detect a case when output color is irrelevant (e.g.,based on an OM state and/or the src alpha, or the like) and skip therest of the shader code that calculates the color.

Embodiments may implement a graphics driver stack designed to compilethe pixel shader regardless of a particular OM state. Such a graphicsdriver stack may not try to enhance or generate code for certain statecombinations that occur frequently. For example, modern video gamesoften set an OM state to use what is commonly known as the “over”operator, which may be defined by Equation (1) as follows:

Destcolor=Srccolor*Srcalpha+(1−Srcalpha)*Dstcolor  Equation (1)

As seen in Equation (1), when Srcapha is zero, Dstcolor does not change.In other words, when a pixel that is being rendered is fullytransparent, the frame buffer color for that pixel does not change.Embodiments modify the pixel shader compiler to look at the blendingoperation and generate shader code that first computes the alpha valueand skips the code that calculates the color if the alpha valueindicates that the final pixel color will not change. If the OM state isset for the “over” operation, also referred to sometimes as a “SourceAlpha,” the pixel shader compiler generates the code in the followingsequence whenever possible:

-   -   1. Code that calculates src_alpha;    -   2. Check if src_alpha==0;    -   3. If #2 is true, the compiler can return some default value        without evaluating the color; and    -   4. If #2 is false; the compiler generates the code that        evaluates the src_color.        Examples of this are provided below with respect to FIGS. 16 to        17.

Turning more specifically to FIG. 16 and the logic flow 1600. The logicflow 1600 performs conditional compilation based on the OM State to skipshading whenever applicable.

Logic flow 1600 can begin at decision block 1602. At decision block 1602“OM state set to src_alpha?” the shader compiler 1024 can determinewhether the OM state is set to src_alpha. From decision block 1602, thelogic flow 1600 can continue to either block 1604 or block 1606. Inparticular, the logic flow 1600 can continue from decision block 1602 toblock 1604 based on a determination that the OM state is set tosrc_alpha while the logic flow 1600 can continue to block 1606 based ona determination that OM state is set to src_alpha.

At block 1604 “compile pixel shader with enhanced branch,” the shadercompiler 1024 can compile the pixel shader with an enhanced branch. Atblock 1606 “compile pixel shader normally,” the shader compiler 1024 cancompile the pixel shader normally (e.g., without an enhanced branch, orthe like).

From block 1604 and 1606, the logic flow 1600 can continue to block 1608“bind pixel shader,” the shader compiler 1024 can bind the pixel shader.

It is worthy to note, that logic flow 1600 is described in the contextof an “over” operator. However, the logic flow is equally applicable toother cases where output color is determined. For example, withoutlimitation, the logic flow 1600 can be implemented to enhance a shaderwhere: Destcolor=0*Destcolor+SRCalpha*SRCcolor;Destcolor=0*Destcolor+(1−SRCalpha)*SRCcolor (in this case the test toskip the PS would be SRCalpha==1 instead of 0);Destcolor=1*Destcolor+SRCalpha*SRCcolor;Destcolor=1*Destcolor+(1−SRCalpha)*SRCcolor; andDestcolor=SRCalpha*Destcolor+(1−SRCalpha)*SRCcolor (normal blending butwith inversed alpha).

As another example, in cases where SRCcolor is multiplied by(1−SRCalpha) during the blending operation, the shader compiler 1024could generate enhanced shader 1060 to check whether SRCalpha is equalto 1, instead of 0, and skip the shading when it is.

Turning more specifically to FIG. 17 and the logic flow 1700. The shadercompiler 1024 can implement logic flow 1700 to reduce and/or omit reador write operations based on an OM state and an alpha value produced bya shader. Furthermore, where an interval compiler is available, thelogic flow 1700 can save even more pixel shader dispatches and shadingrelative to the logic flow 1600. More specifically, the shader compiler1024 can generate an interval representation of the shader over a tileof pixels (e.g., a n by m block of pixels), and if there is a min/maxfiltering mode supported by sampler, the min and max src_alpha can beevaluated over the tile of pixels.

As depicted, logic flow 1700 can begin at decision block 1702. Atdecision block 1702 “OM state set to src_alpha?” the shader compiler1024 can determine whether the OM state is set to src_alpha. Fromdecision block 1702, the logic flow 1700 can continue to either block1704 or block 1714. In particular, the logic flow 1700 can continue fromdecision block 1702 to block 1704 based on a determination that the OMstate is set to src_alpha while the logic flow 1700 can continue toblock 1714 based on a determination that OM state is set to src_alpha.

At block 1704 “compile pixel shader with enhanced branch using intervalshading,” the shader compiler 1024 can compile the pixel shader with anenhanced branch using interval shading. In particular, the shadercompiler 1024 can determine alpha_min and alpha_max.

Continuing to block 1706 “bind interval shader” the shader compiler 1024can bind the interval shader (e.g., the shader compiled at block 1704,or the like). Continuing to decision block 1708 “alpha_max==0?” theshader compiler 1024 can determine whether the alpha-max (e.g., for aparticular tile) is equal to zero. From decision block 1708 the logicflow 1700 can continue to either block 1710 or block 1712. Inparticular, the logic flow 1700 can continue from decision block 1708 toblock 1710 based on a determination that the alpha_max does not equalzero while the logic flow 1700 can continue to block 1712 based on adetermination that alpha_max does equal zero.

More specifically, at blocks 1708, 1710, and 1712, shader compiler 1024can execute the tile shader instead of running the pixel shaders for allthe pixels to determine the alpha_max for an entire tile and bind theinterval shader for the tile where the alpha_max equals zero.

At block 1714 “compile pixel shader normally,” the shader compiler 1024can compile the pixel shader normally (e.g., without an enhanced branch,or the like). The logic flow 1700 can continue to block 1716 “bind pixelshader,” the shader compiler 1024 can bind the pixel shader.

It is worthy to note, if the alpha_max equals zero (e.g., as determinedat decision block 1708, or the like) the shader compiler 1024 can skiplaunching the pixel shades and let the OM use any random value forsrc_color.

Numerous specific details have been set forth herein to provide athorough understanding of the embodiments. It will be understood bythose skilled in the art, however, that the embodiments may be practicedwithout these specific details. In other instances, well-knownoperations, components, and circuits have not been described in detailso as not to obscure the embodiments. It can be appreciated that thespecific structural and functional details disclosed herein may berepresentative and do not necessarily limit the scope of theembodiments.

Some embodiments may be described using the expression “coupled” and“connected” along with their derivatives. These terms are not intendedas synonyms for each other. For example, some embodiments may bedescribed using the terms “connected” and/or “coupled” to indicate thattwo or more elements are in direct physical or electrical contact witheach other. The term “coupled,” however, may also mean that two or moreelements are not in direct contact with each other, but yet stillco-operate or interact with each other.

Unless specifically stated otherwise, it may be appreciated that termssuch as “processing,” “computing,” “calculating,” “determining,” or thelike, refer to the action and/or processes of a computer or computingsystem, or similar electronic computing device, that manipulates and/ortransforms data represented as physical quantities (e.g., electronic)within the computing system's registers and/or memories into other datasimilarly represented as physical quantities within the computingsystem's memories, registers or other such information storage,transmission or display devices. The embodiments are not limited in thiscontext.

It should be noted that the methods described herein do not have to beexecuted in the order described, or in any particular order. Moreover,various activities described with respect to the methods identifiedherein can be executed in serial or parallel fashion.

Although specific embodiments have been illustrated and describedherein, it should be appreciated that any arrangement calculated toachieve the same purpose may be substituted for the specific embodimentsshown. This disclosure is intended to cover any and all adaptations orvariations of various embodiments. It is to be understood that the abovedescription has been made in an illustrative fashion, and not arestrictive one. Combinations of the above embodiments, and otherembodiments not specifically described herein will be apparent to thoseof skill in the art upon reviewing the above description. Thus, thescope of various embodiments includes any other applications in whichthe above compositions, structures, and methods are used.

It is emphasized that the Abstract of the Disclosure is provided tocomply with 37 C.F.R. § 1.72(b), requiring an abstract that will allowthe reader to quickly ascertain the nature of the technical disclosure.It is submitted with the understanding that it will not be used tointerpret or limit the scope or meaning of the claims. In addition, inthe foregoing Detailed Description, it can be seen that various featuresare grouped together in a single embodiment for the purpose ofstreamlining the disclosure. This method of disclosure is not to beinterpreted as reflecting an intention that the claimed embodimentsrequire more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive subject matter lies in lessthan all features of a single disclosed embodiment. Thus the followingclaims are hereby incorporated into the Detailed Description, with eachclaim standing on its own as a separate preferred embodiment. In theappended claims, the terms “including” and “in which” are used as theplain-English equivalents of the respective terms “comprising” and“wherein,” respectively. Moreover, the terms “first,” “second,” and“third,” etc. are used merely as labels, and are not intended to imposenumerical requirements on their objects.

Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims.

EXAMPLE 1

An apparatus to compile a shader comprising: logic, at least a portionof which is implemented in hardware, the logic to: determine whether ashader instruction can output a predetermined value; and compile theshader instruction to include an enhanced sub-sequence based on adetermination that the shader instruction can output the predeterminedvalue.

EXAMPLE 2

The apparatus of example 1, the logic to compile the shader instructionomitting the enhanced sub-sequence based on a determination that theshader instruction cannot output the predetermined value.

EXAMPLE 3

The apparatus of example 1, the logic to: evaluate at least onecoordinate; and determine whether the shader instruction can output thepredetermined value based on the at least one coordinate.

EXAMPLE 4

The apparatus of example 1, wherein the shader instruction comprises asample_c instruction, a mul_sat instruction, an add_sat instruction, ald instruction, a sample instruction, an AND instruction, a greater thaninstruction, an equal to instruction, or a less than instruction.

EXAMPLE 5

The apparatus of example 4, wherein the common value comprises one,zero, 1.0f, 0.0f, or the like.

EXAMPLE 6

The apparatus of example 1, the logic to generate an enhanced shaderbased in part on compiling the shader instructions, the enhanced shaderto: determine whether the output of the shader instruction equals thepredetermined value; and execute a first sequence based on adetermination that the output of the shader instruction equals thepredetermined value; or execute a second sequence based on adetermination that the output of the shader instruction does not equalthe predetermined value, the second sequence requiring more graphicsprocessing resources than the first sequence.

EXAMPLE 7

The apparatus of example 1, the logic to: determine whether the shaderinstruction can be folded based on a determination that the shaderinstruction can output a predetermined value; and compile the shaderinstruction to include the enhanced sub-sequence based on adetermination that the shader instruction can be folded.

EXAMPLE 8

The apparatus of example 7, the logic to compile the shader instructionomitting the enhanced sub-sequence based on a determination that theshader instruction cannot be folded.

EXAMPLE 9

The apparatus of example 1, the logic to: determine whether anoutput-merger (OM) state of the shader instruction is set to asrc_alpha; and compile the shader instruction to include the enhancedsub-sequence based on a determination that the OM state is set tosrc_alpha.

EXAMPLE 10

The apparatus of example 9, the logic to compile the shader instructionomitting the enhanced sub-sequence based on a determination that the OMstate is not set to src_alpha.

EXAMPLE 11

The apparatus of example example 9, the logic to: determine whether analpha-max corresponding to the shader instruction is equal to zero; andbind the shader based on a determination that the alpha_maxcorresponding to the shader instruction equals zero.

EXAMPLE 12

The apparatus of example 1, wherein the compiled shaders comprise apixel shader, a vertex shader, a depth shader, a fragment shader, adomain shader, a hull shader, a computer shader, or a geometry shader.

EXAMPLE 13

A computing-implemented method comprising: determining whether a shaderinstruction can output a predetermined value; and compiling the shaderinstruction to include an enhanced sub-sequence based on a determinationthat the shader instruction can output the predetermined value.

EXAMPLE 14

The method of example 13, comprising compiling the shader instructionomitting the enhanced sub-sequence based on a determination that theshader instruction cannot output the predetermined value.

EXAMPLE 15

The method of example 13, comprising: evaluating at least onecoordinate; and determining whether the shader instruction can outputthe predetermined value based on the at least one coordinate.

EXAMPLE 16

The method of example 13, wherein the shader instruction comprises asample_c instruction, a mul_sat instruction, an add_sat instruction, ald instruction, a sample instruction, an AND instruction, a greater thaninstruction, an equal to instruction, or a less than instruction.

EXAMPLE 17

The method of example 16, wherein the common value comprises one, zero,1.0f, 0.0f, or the like.

EXAMPLE 18

The method of example 13, comprising generating an enhanced shader basedin part on compiling the shader instructions, the enhanced shadercomprising: determining whether the output of the shader instructionequals the predetermined value; and executing a first sequence based ona determination that the output of the shader instruction equals thepredetermined value; or executing a second sequence based on adetermination that the output of the shader instruction does not equalthe predetermined value, the second sequence requiring more graphicsprocessing resources than the first sequence.

EXAMPLE 19

The method of example 13, comprising: determining whether the shaderinstruction can be folded based on a determination that the shaderinstruction can output a predetermined value; and compiling the shaderinstruction to include the enhanced sub-sequence based on adetermination that the shader instruction can be folded.

EXAMPLE 20

The method of example 19, comprising compiling the shader instructionomitting the enhanced sub-sequence based on a determination that theshader instruction cannot be folded.

EXAMPLE 21

The method of example 13, comprising: determining whether anoutput-merger (OM) state of the shader instruction is set to asrc_alpha; and compiling the shader instruction to include the enhancedsub-sequence based on a determination that the OM state is set tosrc_alpha.

EXAMPLE 22

The method of example 21, comprising compiling the shader instructionomitting the enhanced sub-sequence based on a determination that the OMstate is not set to src_alpha.

EXAMPLE 23

The method of example example 22, comprising: determining whether analpha-max corresponding to the shader instruction is equal to zero; andbinding the shader based on a determination that the alpha_maxcorresponding to the shader instruction equals zero.

EXAMPLE 24

The method of example 13, wherein the compiled shaders comprise a pixelshader, a vertex shader, a depth shader, a fragment shader, a domainshader, a hull shader, a computer shader, or a geometry shader.

EXAMPLE 25

An apparatus comprising means for performing the method of any ofexamples 13 to 24.

EXAMPLE 26

At least one machine-readable storage medium comprising instructionsthat when executed by a computing device, cause the computing device to:determine whether a shader instruction can output a predetermined value;and compile the shader instruction to include an enhanced sub-sequencebased on a determination that the shader instruction can output thepredetermined value.

EXAMPLE 27

The at least one machine-readable storage medium of example 26,comprising instructions that when executed by the computing device,cause the computing device to compile the shader instruction omittingthe enhanced sub-sequence based on a determination that the shaderinstruction cannot output the predetermined value.

EXAMPLE 28

The at least one machine-readable storage medium of example 26,comprising instructions that when executed by the computing device,cause the computing device to: evaluate at least one coordinate; anddetermine whether the shader instruction can output the predeterminedvalue based on the at least one coordinate.

EXAMPLE 29

The at least one machine-readable storage medium of example 26, whereinthe shader instruction comprises a sample_c instruction, a mul_satinstruction, an add_sat instruction, a ld instruction, a sampleinstruction, an AND instruction, a greater than instruction, an equal toinstruction, or a less than instruction.

EXAMPLE 30

The at least one machine-readable storage medium of example 29, whereinthe common value comprises one, zero, 1.0f, 0.0f, or the like.

EXAMPLE 31

The at least one machine-readable storage medium of example 26,comprising instructions that when executed by the computing device,cause the computing device to generate an enhanced shader based in parton compiling the shader instructions, the enhanced shader to: determinewhether the output of the shader instruction equals the predeterminedvalue; and execute a first sequence based on a determination that theoutput of the shader instruction equals the predetermined value; orexecute a second sequence based on a determination that the output ofthe shader instruction does not equal the predetermined value, thesecond sequence requiring more graphics processing resources than thefirst sequence.

EXAMPLE 32

The at least one machine-readable storage medium of example 26,comprising instructions that when executed by the computing device,cause the computing device to: determine whether the shader instructioncan be folded based on a determination that the shader instruction canoutput a predetermined value; and compile the shader instruction toinclude the enhanced sub-sequence based on a determination that theshader instruction can be folded.

EXAMPLE 33

The at least one machine-readable storage medium of example 32,comprising instructions that when executed by the computing device,cause the computing device to compile the shader instruction omittingthe enhanced sub-sequence based on a determination that the shaderinstruction cannot be folded.

EXAMPLE 34

The at least one machine-readable storage medium of example 26,comprising instructions that when executed by the computing device,cause the computing device to: determine whether an output-merger (OM)state of the shader instruction is set to a src_alpha; and compile theshader instruction to include the enhanced sub-sequence based on adetermination that the OM state is set to src_alpha.

EXAMPLE 35

The at least one machine-readable storage medium of example 34,comprising instructions that when executed by the computing device,cause the computing device to compile the shader instruction omittingthe enhanced sub-sequence based on a determination that the OM state isnot set to src_alpha.

EXAMPLE 36

The at least one machine-readable storage medium of example 34,comprising instructions that when executed by the computing device,cause the computing device to: determine whether an alpha-maxcorresponding to the shader instruction is equal to zero; and bind theshader based on a determination that the alpha_max corresponding to theshader instruction equals zero.

EXAMPLE 37

The at least one machine-readable storage medium of example 26, whereinthe compiled shaders comprise a pixel shader, a vertex shader, a depthshader, a fragment shader, a domain shader, a hull shader, a computershader, or a geometry shader.

EXAMPLE 38

At least one machine-readable storage medium comprising instructionsthat when executed by a graphics processing unit (GPU), cause the GPUto: evaluate at least one coordinate of pixel; execute a shaderinstruction based on the at least one coordinate; determiner whether anoutput of the shader instruction equals a predetermined value; andexecute a first sequence based on a determination that the output equalsthe predetermined value; or execute an second sequence based on adetermination that the output does not equal the predetermined value.

EXAMPLE 39

The at least one machine-readable storage medium of example 38,comprising instruction that when executed by the GPU, wherein the shaderinstruction comprises a sample_c instruction, a mul_sat instruction, anadd_sat instruction, a ld instruction, a sample instruction, an ANDinstruction, a greater than instruction, an equal to instruction, or aless than instruction.

EXAMPLE 40

The at least one machine-readable storage medium of example 38,comprising instruction that when executed by the GPU, wherein the commonvalue comprises one, zero, 1.0f, 0.0f, or the like.

What is claimed is:
 1. An apparatus to compile a shader comprising:logic, at least a portion of which is implemented in hardware, the logicto: identify a shader instruction as an origin of a predetermined valuebased on analysis of the shader; and compile the shader to include anenhanced sub-sequence to process an output of the predetermined value bythe shader instruction, based on identification of the shaderinstruction as an origin of the predetermined value.
 2. The apparatus ofclaim 1, the logic to compile the shader omitting the enhancedsub-sequence.
 3. The apparatus of claim 1, the logic to: evaluate atleast one coordinate; and determine whether an output of the shaderinstruction is the predetermined value based on the at least onecoordinate.
 4. The apparatus of claim 1, wherein the shader instructioncomprises a sample_c instruction, a mul_sat instruction, an add_satinstruction, a ld instruction, a sample instruction, an AND instruction,a greater than instruction, an equal to instruction, or a less thaninstruction.
 5. The apparatus of claim 4, wherein the predeterminedvalue comprises one or more common values, the common values comprisingone, zero, 1.0f, 0.0f, or the like.
 6. The apparatus of claim 1, thelogic to generate an enhanced shader based in part on compiling theshader instructions, the enhanced shader to: determine whether theoutput of the shader instruction equals the predetermined value; andexecute the enhanced sub-sequence based on a determination that theoutput of the shader instruction equals the predetermined value; orexecute a second sequence based on a determination that the output ofthe shader instruction does not equal the predetermined value, thesecond sequence requiring more graphics processing resources than theenhanced sub-sequence.
 7. The apparatus of claim 1, the logic to:determine whether the shader instruction can be folded based onidentification of the shader instruction as an origin of thepredetermined value; and compile the shader to include the enhancedsub-sequence based on a determination that the shader instruction can befolded.
 8. The apparatus of claim 7, the logic to compile the shaderomitting the enhanced sub-sequence based on a determination that theshader instruction cannot be folded.
 9. The apparatus of claim 1, thelogic to: determine whether an output-merger (OM) state of the shaderinstruction is set to a src_alpha; and compile the shader instruction toinclude the enhanced sub-sequence based on a determination that the OMstate is set to src_alpha.
 10. The apparatus of claim 9, the logic tocompile the shader instruction omitting the enhanced sub-sequence basedon a determination that the OM state is not set to src_alpha.
 11. Theapparatus of claim claim 9, the logic to: determine whether an alpha-maxcorresponding to the shader instruction is equal to zero; and bind theshader based on a determination that the alpha_max corresponding to theshader instruction equals zero.
 12. The apparatus of claim 1, whereinthe shader comprises a pixel shader, a vertex shader, a depth shader, afragment shader, a domain shader, a hull shader, a computer shader, or ageometry shader.
 13. A computing-implemented method comprising:identifying a shader instruction as an origin of a predetermined valuebased on analysis of the shader; and compiling the shader to include anenhanced sub-sequence based identification of the shader instruction asan origin of the predetermined value.
 14. The method of claim 13,comprising: evaluating at least one coordinate; and determining whetherthe shader instruction can output the predetermined value based on theat least one coordinate.
 15. The method of claim 13, wherein the shaderinstruction comprises a sample_c instruction, a mul_sat instruction, anadd_sat instruction, a ld instruction, a sample instruction, an ANDinstruction, a greater than instruction, an equal to instruction, or aless than instruction.
 16. The method of claim 15, wherein thepredetermined value comprises one or more common values, the commonvalues comprising one, zero, 1.0f, 0.0f, or the like.
 17. The method ofclaim 13, comprising: determining whether the shader instruction can befolded based on a determination that the shader instruction can output apredetermined value; and compiling the shader instruction to include theenhanced sub-sequence based on a determination that the shaderinstruction can be folded.
 18. The method of claim 13, comprisingcompiling the shader instruction omitting the enhanced sub-sequence. 19.The method of claim 13, comprising: determining whether an output-merger(OM) state of the shader instruction is set to a src_alpha; andcompiling the shader instruction to include the enhanced sub-sequencebased on a determination that the OM state is set to src_alpha.
 20. Atleast one machine-readable, non-transitory storage medium comprisinginstructions that when executed by a computing device, cause thecomputing device to: identify a shader instruction as an origin of apredetermined value based on analysis of the shader; and compile theshader to include an enhanced sub-sequence to process an output of thepredetermined value by the shader instruction, based on identificationof the shader instruction as an origin of the predetermined value. 21.The at least one machine-readable, non-transitory storage medium ofclaim 20, comprising instructions that when executed by the computingdevice, cause the computing device to: evaluate at least one coordinate;and determine whether the shader instruction can output thepredetermined value based on the at least one coordinate.
 22. The atleast one machine-readable, non-transitory storage medium of claim 20,wherein the shader instruction comprises a sample_c instruction, amul_sat instruction, an add_sat instruction, a ld instruction, a sampleinstruction, an AND instruction, a greater than instruction, an equal toinstruction, or a less than instruction.
 23. At least onemachine-readable, non-transitory storage medium comprising instructionsthat when executed by a graphics processing unit (GPU), cause the GPUto: evaluate at least one coordinate of pixel; execute a shaderinstruction based on the at least one coordinate; determine whether anoutput of the shader instruction equals a predetermined value; andexecute a first sequence based on a determination that the output equalsthe predetermined value; or execute a second sequence based on adetermination that the output does not equal the predetermined value.24. The at least one machine-readable, non-transitory storage medium ofclaim 23, comprising instruction that when executed by the GPU, whereinthe shader instruction comprises a sample_c instruction, a mul_satinstruction, an add_sat instruction, a ld instruction, a sampleinstruction, an AND instruction, a greater than instruction, an equal toinstruction, or a less than instruction.
 25. The at least onemachine-readable, non-transitory storage medium of claim 23, comprisinginstruction that when executed by the GPU, wherein the predeterminedvalue comprises one or more common values, the common values comprisingone, zero, 1.0f, 0.0f, or the like.